- Earnings numbers tell a story not just of surging demand but of structural bottlenecks, tariff-driven cost recalibration, and the quiet emergence of self-reliance blocs that will define semiconductor supply chains for the rest of the decade.
- Pax Silica signals a structural shift: for the remainder of the decade, self-reliance blocs — not free trade — will govern how chips are designed, manufactured, and distributed.
The AI infrastructure build-out has entered a fundamentally new chapter. What began as a race for compute has morphed into something far more complex: a multi-front scramble for memory, advanced-node capacity, power, and geopolitical positioning?
This earnings season, the numbers tell a story not just of surging demand — that much was expected — but of structural bottlenecks, tariff-driven cost recalibration, and the quiet emergence of self-reliance blocs that will define semiconductor supply chains for the rest of the decade.
If there were any doubts that AI accelerators are as memory-hungry as they are compute-hungry, the second quarter of 2026 earnings put them to rest. SK Hynix posted a 397.5 per cent year-on-year surge in net income, while Samsung’s net income soared 486.7 per cent. Both are riding a high-bandwidth memory (HBM) shortage so severe that DRAM capacity is effectively sold out through 2026 and well into 2027.
Micron delivered the most eye-catching number of the season: a 1,398.3 per cent net income explosion on 345.7 per cent revenue growth. Those figures confirm what supply-chain analysts have been warning for quarters — the memory side of the AI equation was underestimated, and the industry is still racing to catch up.
Only three companies globally — SK Hynix, Samsung, and Micron — produce HBM at volume, and all three have allocated their projected 2027 output under multi-year supply agreements. For hyperscalers and enterprises alike, memory availability, not just GPU allocation, now determines how fast AI clusters can be deployed.
The memory crunch has real pricing consequences. DRAM prices reportedly rose approximately 90 per cent in the first quarter of 2026 alone, adding a significant cost layer to every AI training and inference cluster being assembled this year.
Compute titans
NVIDIA’s net income more than tripled, rising 210.6 per cent on relentless data-center demand. But the more telling figure lies beneath the headline: operating cash flow grew 83.6 per cent, while capex — down 70.9 per cent quarter-on-quarter yet up 43.2 per cent year-on-year — reveals how much cash is being redirected into supply-chain commitments.
Among those commitments: securing additional TSMC capacity for H200 production, a strategic move that underscores how even the dominant GPU player must now compete for fab allocation.
TSMC itself posted 77.4 per cent net income growth against a 33.8 per cent year-on-year capex rise, a ratio that reflects the urgency of its advanced-node expansion. Capacity for leading-edge nodes remains tight, and with HBM, logic, and packaging all converging on the same constrained manufacturing ecosystem, the foundry giant’s ability — or inability — to add capacity will cascade across the entire AI supply chain.
Binding constraint hyperscalers can’t ignore
Perhaps the most unexpected headline of the season belongs to Constellation Energy, whose 1,247.5 per cent net income growth highlights a reality that hyperscalers have made explicit on recent earnings calls: power, not chips, is now the binding constraint on AI deployment.
Data centers housing tens of thousands of accelerators require energy at a scale that grid infrastructure was never designed to support, and the lead times for new power capacity — substations, transmission lines, generation — far exceed those for chip fabrication.
This power bottleneck is reshaping site-selection strategies and pushing hyperscalers toward markets with available grid capacity, even if those locations come with higher land, labour, or latency costs.
The outliers
Two companies break from the boom narrative, each in instructive ways. Intel’s net loss narrowed 278.1 per cent year-on-year, and while the company remains deep in turnaround territory, there are genuine signs of life.
The 18A process node reached high-volume manufacturing in January 2026 at Fab 52 in Arizona, with yields improving approximately 7 per cent monthly and reportedly in the 55–65 per cent range — sufficient to ship the Panther Lake platform for AI PCs.
On the balance sheet, Intel’s 9.9 per cent CHIPS Act equity stake has appreciated on paper, and NVIDIA, Microsoft, Amazon, and Apple have all opened foundry discussions. Still, Intel does not expect meaningful foundry revenue before 2027, leaving the turnaround a story of promise rather than proof.
Marvell tells a different cautionary tale. Despite 27.6 per cent revenue growth driven by custom-silicon demand, net income fell 80.6 per cent year-on-year. The squeeze illustrates a structural reality of the custom-ASIC market: ramp costs on leading-edge nodes can overwhelm margins, even when demand is strong.
As hyperscalers increasingly turn to in-house silicon designs, the suppliers building those chips face a profitability paradox — revenue up, earnings down — that may persist until volumes reach critical mass.
Hyperscaler capex
The real story of this earnings season, however, sits not in the semiconductor suppliers’ results but in their customers’ spending plans. Microsoft, Alphabet, and Meta each posted capex growth above 65 per cent year-on-year.
Alphabet has raised its 2026 spending guidance to $175–$190 billion, Meta to $125–$145 billion, and Microsoft toward $120–$190 billion. Combined, the four hyperscalers — adding Amazon, whose first quarter of 2026 alone saw a share of the roughly $130 billion in combined quarterly capex — are on pace for roughly $700–$725 billion in 2026 capital expenditure.
That represents an increase of approximately 77 per cent from 2025 levels, making this the largest peacetime capital cycle in corporate history. Critically, these commitments are being funded even as free cash flow tightens, signaling that hyperscaler leadership views AI infrastructure not as discretionary spending but as existential investment — a conviction that shows no sign of wavering despite the extraordinary sums involved.
Independent estimates put the range even higher: Goldman Sachs models baseline annual AI capex of $765 billion in 2026, while CreditSights projects approximately $750 billion.
Geopolitics embedded in numbers
What distinguishes this cycle from previous technology build-outs is the extent to which geopolitics is now embedded directly in the financials.
In January 2026, the Trump administration invoked Section 232 of the Trade Expansion Act to impose a 25 per cent tariff on a narrow category of advanced AI chips, including the NVIDIA H200 and AMD MI325X, effective January 15–18, 2026.
The proclamation includes a two-phase plan that could raise rates further while creating incentives for domestic semiconductor production.
Simultaneously, the Bureau of Industry and Security (BIS) shifted its export licensing policy for H200 and MI325X chips destined for China and Macau from presumptive denial to case-by-case review, effective January 15, 2026.
This partial reopening caps shipments at roughly 50 per cent of prior US sales volumes — a meaningful change, but one that still left Chinese buyers like ByteDance, Alibaba, and Tencent able to secure only a fraction of the more than two million H200 units they had ordered.
Adding another layer, TSMC, Samsung, and SK Hynix lost their blanket Validated End-User exemptions on January 1, 2026, and must now apply for annual US licenses to ship equipment into their China-based fabrication facilities. This regulatory shift imposes ongoing administrative friction on the world’s three most advanced semiconductor manufacturers.
The broadest geopolitical framework arrived in December 2025 with Pax Silica, the US-led pact signed by two dozen nations — including India, Japan, South Korea, and the Philippines — at the inaugural Pax Silica Summit in Washington, D.C.
The initiative aims to build a secure, resilient, and innovation-driven silicon supply chain outside China’s orbit, covering not just semiconductor fabrication but the critical minerals and advanced packaging that underpin it.
Pax Silica signals a structural shift: for the remainder of the decade, self-reliance blocs — not free trade — will govern how chips are designed, manufactured, and distributed.
India’s ascent
India emerges as a direct beneficiary of this reordering. Micron’s assembly, test, marking, and packaging (ATMP) facility in Sanand, Gujarat, was inaugurated by Prime Minister Narendra Modi on February 28, 2026.
The $2.75 billion plant is now packaging DRAM and NAND for Micron’s global supply chain, with output expected to scale from tens of millions of chips in 2026 to hundreds of millions in 2027.
The timing is fortuitous: an India-origin assembly option arrives precisely as DRAM prices surge and buyers seek supply diversification.
Further down the Gujarat coast, the Tata Electronics–PSMC wafer fab at Dholera has passed the 50 per cent completion mark. The Rs91,000 crore ($11 billion) project targets trial production by December 2026 at the 28nm node, with a designed capacity of up to 50,000 wafer starts per month.
While 28nm is mature by global leading-edge standards, it is more than sufficient to reduce India’s reliance on imported logic and power-management chips — components essential to the country’s electronics manufacturing ambitions. Plans are already in motion for a second fab targeting 14nm and eventually more advanced nodes.