- Samsung’s wafer-bonding technology, if commercialised successfully, could allow the company to leapfrog in both HBM and NAND.
Samsung Electronics introduced a trio of next-generation memory technologies at the Future of Memory and Storage conference on Tuesday. The company revealed a 400-layer NAND flash prototype with two concept architectures to reshape how AI stores and accesses data.
At Silicon Valley’s annual industry gathering, the announcements signal the chipmaker’s resolve to stay ahead. AI workloads evolve from training models to running them at scale, underscoring the aim to extend the memory lead.
Samsung highlighted the V10 Bonding V-NAND, or BV-NAND, as the keynote. This is the industry’s first NAND flash chip to stack over 400 layers vertically. The prototype introduces a new wafer-bonding architecture. Separately fabricated cell and peripheral wafers are fused. This represents a shift away from monolithic designs of earlier generations.
Samsung said BV-NAND delivers roughly 58 per cent increase in bit density versus the current V9 NAND. It also offers faster read and write speeds and improved input/output performance. Higher density enables more data to fit the same physical footprint. It remains a key metric for AI data centres under construction.
AI workloads are shifting, making NAND flash memory increasingly vital. This memory stores photos, videos, and applications across devices from smartphones to server farms. Initially, the race to train large language models valued high-bandwidth DRAM. Daily query answering requires vast pools of high-capacity, power-efficient storage.
Samsung executives told analysts last week that long-term supply agreements with major customers could eventually account for 60 per cent to 70 per cent of the company’s memory revenue; a figure that underscores how deeply AI demand is restructuring the chip industry’s traditionally cyclical business.
Memory that sits on top of processor
Beyond the BV-NAND prototype, Samsung showed concept models of what it described as the industry’s first zHBM and zNAND-O architectures — a vision for 3D memory that stacks cells directly above AI processors rather than placing them alongside.
Conventional high-bandwidth memory, or HBM, sits on an interposer next to an AI accelerator such as a GPU. Data must travel laterally across that bridge, a journey that consumes power and generates heat.
Samsung’s zHBM flips the geometry. By bonding memory vertically on top of the logic die, the distance data travels shrinks dramatically. The company said its wafer-bonding approach could deliver more than 10 times the memory density of standard HBM5 while tripling energy efficiency and cutting thermal resistance by more than half.
The concept remains in early development, and Samsung did not provide a timeline for commercialisation. But the architectural direction reflects a broader industry acknowledgement that traditional chip packaging is reaching physical limits as AI models grow larger.
The zNAND-O concept applies a similar stacking philosophy to NAND storage, laying the groundwork for storage-class memory that sits closer to compute.
Competitive stakes
The FMS conference has become a showcase for the escalating rivalry between Samsung and hometown competitor SK Hynix, which also presented AI memory innovations at the event. SK Hynix currently dominates the HBM market and supplies the memory used in Nvidia’s most advanced AI accelerators.
Samsung’s wafer-bonding technology, if commercialised successfully, could allow the company to leapfrog in both HBM and NAND, analysts said. Pulling it off will require solving formidable manufacturing challenges — wafer bonding at scale remains a technically demanding process.